The present invention relates to apparatus and methods for providing an output signal proportional to the root-mean-square (RMS) value of an input signal. More particularly, the present invention relates to apparatus and methods for providing an output signal proportional to the RMS value of an input signal having a bipolar signal range. The output signal may be a continuous-time direct current (DC) signal proportional to the RMS value of an input signal (commonly called RMS-to-DC conversion), or may be a digital signal that has a value that is proportional to the RMS value of an input signal.
The RMS value of a waveform is a measure of the heating potential of the waveform. RMS measurements allow the magnitudes of all types of voltage (or current) waveforms to be compared to one another. Thus, for example, an alternating current (AC) waveform having a value of 1 volt RMS produces the same amount of heat in a resistor as a 1 volt DC voltage.
Mathematically, the RMS value of a signal V is defined as:
Vrms={square root over ({overscore (V2+L )})}xe2x80x83xe2x80x83(1)
which involves squaring the signal V, computing the average value (represented by the overbar in equation (1)), and then determining the square root of the result.
Various previously known techniques have been used to measure RMS values. In one previously known technique, an applied signal is converted to heat, and a DC output signal is generated that has the same heat potential as the applied signal. For example, the LT1088 Wideband RMS-DC Converter Building Block (LT1088), from Linear Technology Corporation, Milpitas, Calif., may be used with external circuitry (e.g., two matched resistors and an opamp) to provide a thermally-based RMS-to-DC converter circuit. In particular, the LT-1088 includes a first heater having first and second terminals thermally coupled to a first temperature sensing diode, and a second heater having first and second terminals thermally coupled to a second temperature sensing diode. The first heater and first temperature sensing diode are thermally isolated from the second heater and second temperature sensing diode.
An RMS-to-DC converter circuit may be provided using the LT-1088 by coupling: (1) an input signal to the first terminal of the first heater; (2) the second terminals of the first and second heaters and the cathode terminals of the first and second temperature sensing diodes to GROUND; (3) the anode terminal of the first temperature sensing diode to an inverting input of an external opamp and through a first external resistor to a positive power supply (e.g., V+); (4) the anode terminal of the second temperature sensing diode to a non-inverting input of the external opamp and through a second external resistor to V+; and (5) the output of the external opamp to the first terminal of the second heater. The first heater converts the input signal to heat, and the second heater converts the output signal to heat. The external opamp provides a DC output signal having the same heat potential as the input signal.
Thermal techniques such as converter circuits that include the LT1088 provide an accurate result and provide a very high input signal bandwidth. The heaters and temperature sensitive diodes included on the LT1088, however, are sensitive to temperature gradients caused by other circuitry. Therefore, it is difficult to include other circuits (e.g., the opamp or the first and second resistors) on the same die as the circuit inside the LT1088, because the other circuitry would generate temperature gradients that would affect the temperature sensitive diodes. As a result, the LT1088 must be combined with external circuitry to form an RMS-to-DC converter circuit, and it is difficult to implement such thermally-based RMS-to-DC converter circuits on a single integrated circuit.
Another previously known technique for measuring RMS values utilizes the exponential current-voltage relationship of a forward-biased semiconductor junction, and commonly is referred to as log-antilog RMS-to-DC conversion. In particular, a transconductance circuit converts an input voltage to an input current, a first forward-biased semiconductor junction conducts the input current and produces a first voltage (proportional to the natural logarithm of the input current), a multiplier circuit doubles the first voltage (equivalent to squaring the input current), a lowpass filter provides a second voltage proportional to the average value of the first voltage, a divider circuit halves the second voltage (equivalent to taking the square-root of the averaged, squared input current), and the halved second voltage is applied across a second forward-biased semiconductor junction to produce an output current proportional to the square-root of the average of the squared input current.
Because the input to any logarithm computation must be positive, conventional log-antilog RMS-to-DC converter circuits require a preceding absolute value circuit to assure that the input current remains positive. Because the heating potential of a signal depends on the signal amplitude and not the signal polarity, the absolute value operation ideally does not alter the RMS value of the signal.
Log-antilog RMS-to-DC converters, however, have several disadvantages. First, the amplitude of the signals conducted by the forward-biased semiconductor junctions are much smaller than conventional signal levels. As a result, all errors caused by component tolerances, thermal drift, mechanical stress and other factors are enhanced. Second, an absolute value circuit is difficult to implement because the circuit typically contributes offset, polarity gain mismatch and frequency-dependent and amplitude-dependent errors. Third, actual forward-biased semiconductor junctions have current-voltage relationships that deviate from an ideal exponential relationship, and therefore further limit the accuracy of the RMS-to-DC converter circuit.
Another known RMS-to-DC converter circuit is described in U.S. Pat. No. 5,896,056 to Glucina, the disclosure of which is incorporated by reference in its entirety. FIG. 1 illustrates an exemplary embodiment of Glucina""s RMS-to-DC converter circuits. In particular, circuit 10 includes rectifier 12, modulator 14, demodulator 16, lowpass filter 18, and optional gain stages 20 and 22. Gain stage 20 has a gain A and gain stage 22 has a gain B. Gain stages 20 and 22 may be included together, included individually, or omitted entirely from circuit 10. Rectifier 12 is coupled to input signal VIN and provides rectified output signal VY. VIN is a bipolar signal, i.e., VIN has an instantaneous magnitude that may be positive or negative. Rectifier 12 converts VIN to time-varying signal VY that is a monopolar signal, i.e., VY has an instantaneous magnitude that is only positive or only negative. VY ideally is the instantaneous absolute value of VIN, and the RMS value of VY ideally equals the RMS value of VIN:
{square root over ({overscore (VIN2+L )})}={square root over ({overscore (VY2+L )})}xe2x80x83xe2x80x83(2)
where {overscore (VIN2 +L )} is the mean value of VIN2, and {overscore (VY2 +L )} is the mean value of VY2.
Modulator 14 is a pulse code modulator that has a monopolar input signal range and has an input terminal coupled to VY, a reference terminal coupled to the output of gain stage 22, and an output terminal that provides pulse code modulated (PCM) output signal D having a duty ratio equal to the ratio of VY to Bxc3x97VOUT:                     D        =                              V            Y                                B            xc3x97                          V              OUT                                                          (        3        )            
An example of a pulse modulator used to implement a division function is described, for example, by Dan Harres, xe2x80x9cPulse Modulated Divider Suits Multichannel Systems,xe2x80x9d EDN, Mar. 15, 1990 (hereinafter referred to as xe2x80x9cHarresxe2x80x9d). An implementation of a division function using a pulse modulator also is described in more detail below.
PCM output signal D may, for example, comprise a stream of binary pulses, wherein each pulse is a binary signal (e.g., a digital signal having values LOW and HIGH) having a fixed pulse period. The duty ratio over a predetermined interval (e.g., 10 pulse periods) equals the ratio of the number pulses having a value HIGH during that interval to the total number of pulse periods during that interval. Thus, for example, if a pulse stream contains 4 pulses having a value HIGH during an interval of 10 pulse periods, the duty ratio equals 4/10=40%.
For high accuracy, modulator 14 may be implemented using an oversampling xcex94-xcexa3 pulse code modulator, as is known in the art. xcex94-xcexa3 modulators advantageously provide inherently good linearity and accuracy that is set by over-sampling ratios. For example, with an over-sampling ratio of 2000:1, a first-order xcex94-xcexa3 modulator has a signal-to-noise ratio that approaches 90 dB. xcex94-xcexa3 modulators, however, also have imperfections called limit cycles and idle tones that degrade performance.
Demodulator 16 has a monopolar input signal range and has an input terminal coupled to VY, a control terminal coupled to modulator output signal D, and an output terminal that provides demodulator output signal VX that is proportional to the product of VY and the duty ratio of PCM output signal D. In particular. demodulator 16 may comprise a switch that xe2x80x9cchopsxe2x80x9d VY at a rate controlled by PCM output signal D. As a result, demodulator output signal VX has a magnitude equal to the product of VY and D:                               V          X                =                              D            xc3x97                          V              Y                                =                                                                      V                  Y                                                  B                  xc3x97                                      V                    OUT                                                              xc3x97                              V                Y                                      =                                          V                Y                2                                            B                xc3x97                                  V                  OUT                                                                                        (        4        )            
An example of such a demodulator circuit is described in Harres.
The duty ratio of PCM output signal D must be within the range 0% to 100%. Because the duty ratio of D is proportional to the ratio of VY to VOUT, and because VOUT must be positive, the lower limit (i.e., D=0%) requires that VY must be greater than or equal to zero. The upper limit (i.e., D=100%) requires that the peak magnitude of VY not exceed Bxc3x97VOUT.
Lowpass filter 18 has a monopolar input signal range and provides output VZ equal to the time average of input signal VX. Lowpass filter 18 has a narrow passband, such that VZ is a quasi-static DC voltage that may be expressed as:                               V          z                =                  AVG          ⁢                      xe2x80x83                    ⁢                      (                                          V                Y                2                                            B                xc3x97                                  V                  OUT                                                      )                                              (        5        )            
where AVG represents the time average.
Output signal VOUT equals:                               V          OUT                =                              A            xc3x97                          V              z                                =                      A            xc3x97            AVG            ⁢                          xe2x80x83                        ⁢                          (                                                V                  Y                  2                                                  B                  xc3x97                                      V                    OUT                                                              )                                                          (        6        )            
Because VZ is a quasi-static DC value, VOUT also is a quasi-static DC value that has a time average approximately equal to VOUT. As a result, equation (6) can be written as:                               V          OUT                =                              A            B                    xc3x97                                                    V                Y                2                            _                                      V              OUT                                                          (        7        )            
where VY2 is the time-average of VY2. Equation (7) may be re-written as:
VOUT2=A/Bxc3x97{overscore (VY2+L )}xe2x80x83xe2x80x83(8)
According, VOUT equals:                               V          OUT                =                                                            A                B                                      xc3x97                                                            V                  Y                  2                                _                                              =                                                    A                B                                      xc3x97                                                            V                  IN                  2                                _                                                                        (9a)                                =                                            A              B                                xc3x97                      V                          R              ⁢                              xe2x80x83                            ⁢              M              ⁢                              xe2x80x83                            ⁢              S                                                          (9b)            
The overall gain of circuit 10 equals VOUT/VRMS, which equals the square root of A/B.
Absolute value circuit 12 provides an output VY equal to the absolute value of input VIN, so that the input to modulator always is non-negative. Absolute value circuits, however, are difficult to implement and may impose gain errors and speed limitations that may degrade the performance of circuit 10, particularly the accuracy with which output VOUT of circuit 10 approximates the value shown in equation (9b).
In addition, circuit 10 is not easily implemented in integrated circuit form. In particular, if modulator 14 is a xcex94-xcexa3 modulator, the circuit is best implemented in complementary metal oxide semiconductor (CMOS) technology. Absolute value circuit 12, however, is best implemented in bipolar technology. Thus, it is difficult to fabricate circuit 10 as a single integrated circuit in a single technology.
Thus, to improve Glucina""s circuits, it would be desirable to provide methods and apparatus for performing RMS-to-DC conversion of input signals having a bipolar signal range.
It also would be desirable to provide methods and apparatus for performing RMS-to-DC conversion that do not require a preceding absolute value circuit.
It also would be desirable to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits that can be implemented using a single integrated circuit technology.
It still further would be desirable to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits implemented using a CMOS technology.
It also would be desirable to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits implemented using digital circuitry.
It still further would be desirable to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits implemented using switched-capacitor circuitry.
It further would be desirable to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits that include xcex94-xcexa3 modulators, but that reduce or eliminate limit cycles and idle tones.
Accordingly, it is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversion of input signals having a bipolar signal range.
It also is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversion that do not require a preceding absolute value circuit.
It also is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits that can be implemented using a single integrated circuit technology.
It still further is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits implemented using a CMOS technology.
It also is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits implemented using digital circuitry.
It further is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits implemented using switched-capacitor circuitry.
It further is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversion with converter circuits that include xcex94-xcexa3 modulators, but that reduce or eliminate limit cycles and idle tones.
In accordance with these and other objects of the present invention, converter circuits in accordance with this invention include a pulse modulator and a demodulator each having a bipolar input signal range. The pulse modulator may be any commonly known pulse modulator, such as a pulse code modulator, pulse width modulator, or other similar modulator. Preferably, the pulse modulator is a single-bit oversampling xcex94-xcexa3 pulse code modulator. If the modulator is a xcex94-xcexa3 pulse code modulator, the demodulator may be implemented using a multiplying digital-to-analog converter.
Converter circuits in accordance with this invention may include first and second gain stages, the first gain stage provided in an input signal path of the pulse modulator, the second gain stage provided in an input or output signal path of the demodulator, the first and second gain stages providing first and second gains, respectively, the first and second gains selected so that the overall gain of the converter substantially is unity (1.0) or other integer value. In addition, the modulator may be a xcex94-xcexa3 modulator and the first and second gains may be selected to minimize idle tones and limit cycles in the modulator.
Converter circuits in accordance with this invention may be implemented on a single integrated circuit, using continuous-time, switched-capacitor, or digital circuitry, or using combinations of such circuitry. In particular, converter circuits of this invention may be implemented using switched-capacitor CMOS technology.